Accelerating Visual Analytics across the Memory and Storage Stack

Vijaykrishnan Narayanan
Pennsylvania State University

Abstract

First, I will present a Look-Up Table (LUT) based Processing-In-Memory (PIM) technique with the potential for running Neural Network inference tasks.  The proposed LUT-based PIM methodology exploits substantial parallelism using look-up tables that preserve the bit-cell and peripherals of the existing SRAM monolithic arrays in processor caches. Next, I will present GaaS-X, a graph analytics accelerator that inherently supports sparse graph data representations using in-situ compute-enabled crossbar memory architectures. The proposed design alleviates the overheads of redundant writes, sparse to dense conversions, and redundant computations on the invalid edges that are present in other state-of-the-art crossbar-based PIM accelerators. Finally, I will present an in-SSD key-value database that uses the embedded CPU core, and DRAM memory on the SSD to support various queries with predicates and reduce the data movement between SSD and host processor significantly.

[Slides]

Bio

Vijaykrishnan Narayanan is the A. Robert Noll Chair Professor of Computer Science & Engineering and Electrical Engineering at the Pennsylvania State University. Vijay received his Bachelors in Computer Science & Engineering from University of Madras, India in 1993 and his Ph.D. in Computer Science & Engineering from the University of South Florida, USA, in 1998. He is a co-director of the Microsystems Design Lab. He is a Fellow of the National Academy of Inventors, IEEE and ACM. [Source]